Methods Of Forming Metal Gate Spacer

ABSTRACT

A method includes providing dummy gate structures disposed over a device region and over an isolation region adjacent the active region, first gate spacers disposed along sidewalls of the dummy gate structures in the active region, and second gate spacers disposed along sidewalls of the dummy gate structures in the isolation region, removing top portions of the second, but not the first gate spacers, forming a first dielectric layer over the first gate spacers and remaining portions of the second gate spacers, replacing the dummy gate structures with metal gate structures after the forming of the first dielectric layer, removing the first gate spacers after the replacing of the dummy gate structures, and forming a second dielectric layer over top surfaces of the metal gate structures and of the first dielectric layer.

PRIORITY DATA

This is a divisional application of and claims priority to U.S. patentapplication Ser. No. 16/218,330 filed on Dec. 12, 2018, which claimspriority to U.S. Provisional Patent Application Ser. No. 62/691,092filed on Jun. 28, 2018, the entire disclosures of which are incorporatedherein by reference.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experiencedexponential growth. Technological advances in IC materials and designhave produced generations of ICs where each generation has smaller andmore complex circuits than the previous generation. In the course of ICevolution, functional density (i.e., the number of interconnecteddevices per chip area) has generally increased while geometry size(i.e., the smallest component (or line) that can be created using afabrication process) has decreased. This scaling down process generallyprovides benefits by increasing production efficiency and loweringassociated costs. Such scaling down has also increased the complexity ofprocessing and manufacturing ICs.

For example, many methods have been developed to introduce structuralfeatures to fin-like FETs (FinFETs) for improved device performance.While these methods have generally been adequate, they have not beensatisfactory in all aspects.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detaileddescription when read with the accompanying figures. It is emphasizedthat, in accordance with the standard practice in the industry, variousfeatures are not drawn to scale and are used for illustration purposesonly. In fact, the dimensions of the various features may be arbitrarilyincreased or reduced for clarity of discussion.

FIG. 1A is a perspective view of an embodiment of a semiconductor deviceaccording to various aspects of the present disclosure.

FIG. 1B is a planar top view of an embodiment of a semiconductor deviceaccording to various aspects of the present disclosure.

FIG. 2 is a flow chart of a method of fabricating a semiconductor deviceaccording to various aspects of the present disclosure.

FIGS. 3, 4, 5, 6, 7, 8, and 9 are cross-sectional views of an embodimentof the semiconductor device of FIGS. 1A and 1B taken along dashed lineAA′ during intermediate steps of an embodiment of the method of FIG. 2according to various aspects of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the disclosure.Specific examples of components and arrangements are described below tosimplify the present disclosure. These are, of course, merely examplesand are not intended to be limiting. For example, the formation of afirst feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

In addition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.Moreover, the formation of a feature on, connected to, and/or coupled toanother feature in the present disclosure that follows may includeembodiments in which the features are formed in direct contact, and mayalso include embodiments in which additional features may be formedinterposing the features, such that the features may not be in directcontact. In addition, spatially relative terms, for example, “lower,”“upper,” “horizontal,” “vertical,” “above,” “over,” “below,” “beneath,”“up,” “down,” “top,” “bottom,” etc., as well as derivatives thereof(e.g., “horizontally,” “downwardly,” “upwardly,” etc.) are used for easeof the present disclosure of one features relationship to anotherfeature. The spatially relative terms are intended to cover differentorientations of the device including the features. Still further, when anumber or a range of numbers is described with “about,” “approximate,”and the like, the term is intended to encompass numbers that are withina reasonable range including the number described, such as within +/−10%of the number described or other values as understood by person skilledin the art. For example, the term “about 5 nm” encompasses the dimensionrange from 4.5 nm to 5.5 nm.

The present disclosure is generally related to semiconductor devices,and more particularly to field-effect transistors (FETs), such as planarFETs or three-dimensional fin-line FETs (FinFETs). It is an objective ofthe present disclosure to provide high-k metal gate spacers and methodsof making the same during FinFET processes.

During fabrication of a FinFET structure, air gap may be formed in placeof gate spacer disposed on sidewalls of gate structures (e.g., high-kmetal gate structures (HKMGs)). In some embodiments, air gap formedbetween gate structures and additional dielectric layers in activedevice regions decrease capacitance of the gate structures, therebyimproving the overall performance of the FinFET structure. However, whenair gap is formed on sidewalls of gate structures disposed in anisolation region adjacent the active device region, structuralcomplications may be introduced as a result. For example, due todifference in height between gate structures formed in the isolationregion and the active device region, aspect ratio of an air gap formedin the isolation region may be greater than that of an air gap formed inthe active device region. Such difference may lead to collapse of thegate structures and may in turn cause shorting issues between the gatestructures and other conductive components (e.g., source/drain contacts)of the device. For this and other reasons, improvements in the formationof air gap are desired.

FIGS. 1A and 1B illustrate a three-dimensional perspective view and atop view, respectively, of a portion of a semiconductor structure 100.FIG. 2 is a flow chart of a method 200 for processing an embodiment ofthe semiconductor structure 100 according to various aspects of thepresent disclosure. The method 200 is merely an example and is notintended to limit the present disclosure beyond what is explicitlyrecited in the claims. Additional operations can be provided before,during, and after the method 200, and some operations described can bereplaced, eliminated, or moved around for additional embodiments of themethod. Intermediate steps of the method 200 is described below inconjunction with FIGS. 3-9, which each illustrates a cross-section viewof a portion of the semiconductor structure 100 taken along a dashedline AA′ as shown in FIGS. 1A and 1B, according to various aspects ofthe present disclosure.

The semiconductor structure 100 may be an intermediate device fabricatedduring processing of an IC, or a portion thereof, that may comprisestatic random-access memory (SRAM) and/or other logic circuits, passivecomponents such as resistors, capacitors, and inductors, and activecomponents such as p-type FETs (PFETs), n-type FETs (NFETs), FinFETs,metal-oxide semiconductor field effect transistors (MOSFET),complementary metal-oxide semiconductor (CMOS) transistors, bipolartransistors, high voltage transistors, high frequency transistors,and/or other memory cells The present disclosure is not limited to anyparticular number of devices or device regions, or to any particulardevice configurations. For example, though the semiconductor structure100 as illustrated is a three-dimensional FinFET device, the presentdisclosure may also provide embodiments for fabricating planar FETdevices.

Referring collectively to FIGS. 1A-3, the method 200 at operation 202provides the semiconductor structure 100. Referring to FIG. 1A, thesemiconductor structure 100 may include a substrate 110 havingthree-dimensional active regions, hereafter referred to as fins, 120formed thereon, dummy gate structures 140 formed over and engaging thefins 120 on three sides in a channel region of each fin 120, isolationstructures 130 formed over the substrate 110 separating variouscomponents of the semiconductor structure 100, source/drain (S/D)features 122 formed over the fins 120. Referring to FIG. 1B, the dummygate structures 140 are oriented lengthwise along the Y direction andseparated from each other along a direction of the fin length, i.e., theX direction. Specifically, some dummy gate structures 140 are disposedin a device region (alternatively referred to as an active region) 110A,where the dummy gate structures 140 engage the fins 120 in a channelregion of each fin 120. Other dummy gate structures 140 are disposed inan isolation region 110B disposed adjacent to the device region 110A,where the isolation region 110B includes the isolation structure 130. Inmany embodiments, the device region 110A provides multiple FinFETdevices following formation of metal gate structures.

As depicted herein, the semiconductor structure 100 may include multiplefins 120 oriented lengthwise along the X direction and multiple dummygate structure 140 oriented lengthwise along the Y direction, i.e.,generally perpendicular to the fins 120. In many embodiments, as will bediscussed in detail below, the semiconductor structure 100 includesadditional features such as gate spacers disposed along sidewalls of thedummy gate structures 140, hard mask layer(s) disposed over the dummygate structures 140, and numerous other features. For purpose ofsimplicity, intermediate steps of the method 200 are hereafter describedwith reference to cross-sectional views (FIGS. 3-9) of the semiconductorstructure 100 taken along the dashed line AA′ as illustrated in FIGS.1A-1B.

The substrate 110 may comprise an elementary (single element)semiconductor, such as silicon, germanium, and/or other suitablematerials; a compound semiconductor, such as silicon carbide, galliumarsenic, gallium phosphide, indium phosphide, indium arsenide, indiumantimonideor, and/or other suitable materials; an alloy semiconductorsuch as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and/orother suitable materials. The substrate 110 may be a single-layermaterial having a uniform composition. Alternatively, the substrate 110may include multiple material layers having similar or differentcompositions suitable for IC device manufacturing. In one example, thesubstrate 110 may be a silicon-on-insulator (SOI) substrate having asemiconductor silicon layer formed on a silicon oxide layer. In anotherexample, the substrate 110 may include a conductive layer, asemiconductor layer, a dielectric layer, other layers, or combinationsthereof.

In some embodiments where the substrate 110 includes FETs, various dopedregions, such as source/drain regions, are formed in or on the substrate110. The doped regions may be doped with p-type dopants, such asphosphorus or arsenic, and/or n-type dopants, such as boron or indium,depending on design requirements. The doped regions may be formeddirectly on the substrate 110, in a p-well structure, in an n-wellstructure, in a dual-well structure, or using a raised structure. Dopedregions may be formed by implantation of dopant atoms, in-situ dopedepitaxial growth, and/or other suitable techniques.

The fins 120 may be fabricated using suitable processes includingphotolithography and etch processes. The photolithography process mayinclude forming a photoresist layer (resist) overlying the substrate110, exposing the resist to a pattern, performing post-exposure bakeprocesses, and developing the resist to form a masking element (notshown) including the resist. The masking element is then used foretching recesses into the substrate 110, leaving the fins 120 on thesubstrate 110. The etching process may include dry etching, wet etching,reactive ion etching (RIE), and/or other suitable processes.

Numerous other embodiments of methods for forming the fins 120 may besuitable. For example, the fins 120 may be patterned usingdouble-patterning or multi-patterning processes. Generally,double-patterning or multi-patterning processes combine photolithographyand self-aligned processes, allowing patterns to be created that have,for example, pitches smaller than what is otherwise obtainable using asingle, direct photolithography process. For example, in one embodiment,a sacrificial layer is formed over a substrate and patterned using aphotolithography process. Spacers are formed alongside the patternedsacrificial layer using a self-aligned process. The sacrificial layer isthen removed, and the remaining spacers, or mandrels, may then be usedto pattern the fins.

The isolation structures 130 may include silicon oxide, silicon nitride,silicon oxynitride, fluoride-doped silicate glass (FSG), a low-kdielectric material, and/or other suitable materials. The isolationstructures 130 may include shallow trench isolation (STI) features. Inone embodiment, the isolation structures 130 are formed by etchingtrenches in the substrate 110 during the formation of the fins 120. Thetrenches may then be filled with an isolating material described above,followed by a chemical mechanical planarization (CMP) process. Otherisolation structure such as field oxide, local oxidation of silicon(LOCOS), and/or other suitable structures may also be implemented as theisolation structures 130. Alternatively, the isolation structures 130may include a multi-layer structure, for example, having one or morethermal oxide liner layers. In some embodiments, such as those depictedin FIGS. 3-9, forming the fins 120 inadvertently removes a portion ofthe isolation structures 130, such that a top surface of the isolationstructures 130 assumes a concave configuration. In other words, in theview depicted herein, a center thickness t_(c) of the isolationstructures 130 is less than an edge thickness t_(e) of the isolationstructures 130. In one example, a ratio of t_(c) to t_(e) may be about0.85. Of course, the present disclosure is not limited to thisconfiguration.

In the device region 110A, the dummy gate structures 140 engage the fins120 in the channel region of each fin 120. In many embodiments, as willbe discussed in detail below, portions of the dummy gate structure 140will be replaced with a high-k metal gate structure (HKMGs) after othercomponents, such as S/D features 122, of the semiconductor structure 100are fabricated. The dummy gate structure 140 includes at least a dummygate electrode comprising polysilicon. Though not depicted herein, thedummy gate structure 140 may include additional material layers, such asan interfacial layer over the fins 120, a dielectric layer, a cappinglayer, other suitable layers, or combinations thereof. In the depictedembodiment, referring to FIG. 3, the dummy gate structures 140 disposedentirely in the device region 110A are referred to as dummy gatestructures 140A, those disposed entirely on the isolation region 110Bare referred to as dummy gate structures 140B, and the dummy gatestructure 140 disposed at a boundary between the regions 110A and 110Bis referred to as dummy gate structure 140C. In many embodiments, anedge of the dummy gate structure 140C substantially coincides with theboundary between the regions 110A and 110B along the Z direction.

In the depicted embodiment, referring to FIG. 3, the dummy gatestructure 140 includes a hard mask layer 144 disposed over the dummygate electrode and a hard mask layer 146 disposed over the hard masklayer 144. In some embodiments, the hard mask layers 144 and 146 areconfigured to protect the dummy gate electrode from subsequentoperations of the method 200. The hard mask layers 144 and 146 may eachinclude any suitable dielectric material, such as a nitrogen-containingdielectric material, an oxygen-containing dielectric material, othersuitable materials, or combinations thereof. In the depicted embodiment,the hard mask layer 144 includes a nitrogen-containing dielectricmaterial, such as silicon nitride or a metal nitride, and the hard masklayer 146 includes an oxygen-containing dielectric material, such assilicon oxide or a metal oxide.

The hard mask layers 144 and 146 and various material layers included inthe dummy gate structure 140 may be formed by any suitable method, suchas chemical oxidation, thermal oxidation, atomic layer deposition (ALD),chemical vapor deposition (CVD), physical vapor deposition (PVD),low-pressure chemical vapor deposition (LP-CVD), plasma-enhanced CVD(PE-CVD), high-density plasma CVD (HDP-CVD), metal organic CVD (MO-CVD),remote plasma CVD (RP-CVD), plasma enhanced CVD (PE-CVD), low-pressureCVD (LP-CVD), atomic layer CVD (AL-CVD), atmospheric pressure CVD(AP-CVD), other suitable methods, or combinations thereof. In oneembodiment, the various layers of the dummy gate structure 140 are firstdeposited as blanket layers. The blanket layers are then patternedthrough a series of lithography and etching processes, thereby removingportions of the blanket layers and keeping the remaining portions overthe isolation structures 130 and the fins 120 as the dummy gatestructure 140.

In many embodiments, because a top surface of the fin 120 extends abovea top surface of the isolation structures 130 (i.e., the fin heighth_(f) measured from a top surface of the isolation structure 130 isgreater than t_(e)), the dummy gate structures 140 disposed in theisolation region 110B are taller than the dummy gate structures 140disposed in the device region 110A, i.e., the height h₂ is greater thanthe height h₁ as depicted in FIG. 3.

Referring to FIG. 3, the semiconductor structure 100 further includes agate spacer layer (or alternatively referred to as “gate spacer”) 152disposed along sidewalls of the dummy gate structures 140 and a gatespacer layer (or alternatively referred to as “gate spacer”) 154disposed over the gate spacer layer 152. In some embodiments, the gatespacer layer 152 may be omitted, such that the gate spacer layer 154directly contacts the dummy gate structures 140. The gate spacer layers152 and 154 have different compositions from each other and eachincludes a material different from the material(s) included in the dummygate structure 140. In some embodiments, the gate spacer layers 152 and154 may include silicon, oxygen, nitrogen, carbon. In one example, thegate spacer layer 152 may include carbon-doped silicon nitride. The gatespacer layers 152 and 154 may differ in composition. For example, thegate spacer layer 152 may include a greater amount of carbon than thegate spacer layer 154. In some embodiments, additional gate spacerlayer(s) may be included between the dummy gate structures 140 and thegate spacer layer 154. The gate spacer layers 152 and 154 may each beformed by first depositing a blanket of spacer material over thesemiconductor structure 100 by a method such as CVD, PVD, ALD, othersuitable methods, or combinations thereof, and then performing ananisotropic etching process to remove portions of the spacer material toform the gate spacer layers 152 and 154.

Still referring to FIG. 3, the semiconductor structure 100 includes S/Dfeatures 122 disposed over the fins 120. The S/D features 122 may beformed by any suitable techniques, such as etching processes followed byone or more epitaxy processes. In one example, one or more etchingprocesses are performed to remove portions of the fins 120 to formrecesses (not shown) therein. A cleaning process may be performed toclean the recesses with a hydrofluoric acid (HF) solution or othersuitable solution. Subsequently, one or more epitaxial growth processesare performed to grow epitaxial features in the recesses. Each of theS/D features 122 may be suitable for a p-type FinFET (e.g., a p-typeepitaxial material) or alternatively, an n-type FinFET (e.g., an n-typeepitaxial material). The p-type epitaxial material may include one ormore epitaxial layers of silicon germanium (epi SiGe), where the silicongermanium is doped with a p-type dopant such as boron, germanium,indium, and/or other p-type dopants. The n-type epitaxial material mayinclude one or more epitaxial layers of silicon (epi Si) or siliconcarbon (epi SiC), where the silicon or silicon carbon is doped with ann-type dopant such as arsenic, phosphorus, and/or other n-type dopants.

Now collectively referring to FIGS. 2, 4, and 5, the method 200 atoperation 204 removes portions of the gate spacer layer 154 withoutsubstantially removing the gate spacer layer 152. Specifically, topportions of the gate spacer layer 154 are selectively removed from theisolation region 110B relative to the gate spacer layer 152, the hardmask layer 144, the hard mask layer 146, and the dummy gate structures140. In some embodiments, the method 200 removes the top portions of thegate spacer layer 154 in a series of patterning and etching processes asdiscussed below.

Referring to FIG. 4, a patterned mask 160 is first formed over thedevice region 110A to expose the isolation region 110B. Forming thepatterned mask 160 may include forming a bottom layer, such as a bottomanti-reflective coating (BARC), over the semiconductor structure 100,and subsequently forming a resist layer (e.g., a photoresist layer; notdepicted) over the bottom layer. The resist layer may be patterned usingany suitable method to form the patterned mask 160 that exposes theisolation region 110B. After the patterning process, the bottom layermay then be removed from the isolation region 110B by any suitablemethod, such as a wet cleaning process utilizing any suitable solvent(e.g., high-temperature sulfuric peroxide mix (HTSPM), dilutehydrofluoric acid (DHF), other suitable solvents, or combinationsthereof). In many embodiments, an edge of the patterned mask 160substantially coincides with an edge of the fin 120 along the Zdirection. In other words, as depicted in FIG. 4, the gate spacer layers152 and 154 on the sidewalls of the dummy gate structure 140C extenddownward along the Z direction to contact the isolation structures 130,such that they are exposed by the patterned mask 160.

Referring to FIG. 5, the method 200 at operation 204 performs an etchingprocess 162 to selective remove top portions of the gate spacer layer154 relative to the gate spacer layer 152, the hard mask layer 144, thehard mask layer 146, and the dummy gate structures 140. In other words,the etching of the gate spacer layer 154 is subjected to a higher etchrate relative to the gate spacer layer 152, the hard mask layer 144, thehard mask layer 146, and the dummy gate structures 140. In someembodiments, the etching process 162 is tuned by controlling etchingpower, duty cycle, duration of etching time, and/or ratio of multipleetchants, such that a height of the remaining portions of the gatespacer layer 154 may be adjusted according to specific designrequirements. In some embodiments, the etching process 162 may implementany suitable etching process, such as a dry etching process, a wetetching process, RIE, other suitable processes, or combinations thereof.In an example embodiment, the etching process 162 implements a dryetching process using one or more suitable etchant, such as afluorine-containing etchant, a chlorine-containing etchant, othersuitable etchants, or combinations thereof. In some embodiments, theetching process 162 is implemented anisotropically along the Zdirection. Following the etching process 162, the patterned mask 160 isremoved from the semiconductor structure 100 by any suitable process,such as plasma ashing or resist stripping.

In the depicted embodiment, remaining portions 184 of the gate spacerlayer 154 are disposed on both sidewalls of the dummy gate structures140B, while a remaining portion 182 of the gate spacer layer 154 isdisposed only on one of the two sidewalls of the dummy gate structure140C. In many embodiments, after performing the etching process 162, aheight h_(s) of the remaining portions 184 is at least about 30% theheight h₂ of the dummy gate structures 140B, and a height h_(p) of theremaining portion 182 is greater than the fin height h_(f). In otherwords, no more than about 70% of the gate spacer layer 154 disposed onsidewalls of the dummy gate structures 140B and 140C may be removed bythe etching process 162, and a top surface of the remaining portions 182and 184 are above the top surface of the fin 120. In furtherembodiments, the height h_(p) may be less than the height h_(s). In oneexample, a ratio of h_(p) to h_(s) is about 0.9 In a further example, adifference between h_(p) and h_(s) is less than about 10 nm. Notably,the height h_(s) is configured to be at least 30% of the height h₂ toensure that the high-k metal gate structures (HKMG) to be formed inplace of the dummy gate structures 140B in the isolation region 110B maynot collapse during the gate replacement process as discussed in detailbelow. Of course, the percentages cited above are example average valuesas the dummy gate structures 140B disposed near the edge of theisolation structures 130 may be lower than those disposed near thecenter of the isolation structures 130 for reasons discussed in detailabove. The height h_(s) and h_(p) may be controlled by tuning theetching time, power, duty cycle, duration, and/or ratio of differentetchants of the etching process 162. For example, to control the heighth_(p) and h_(s), the etching time may be adjusted based on the etchingbehavior of the gate spacer layer 154.

Referring to FIGS. 2 and 6, the method 200 at operation 206 deposits adielectric layer 156 over the device region 110A and the isolationregion 110B. In many embodiments, the method 200 deposits the dielectriclayer 156 over the dummy gate structures 140, the fin 120, and theisolation structure 130, such that the dielectric layer 156 is formedconformally over the dummy gate structures 140 (i.e., the dummy gatestructures 140A, 140B, and 140C). In some embodiments, the dielectriclayer 156 is configured to protect the underlying structures from beingdamaged during subsequent processing steps and may be, for example, acontact etch-stop layer (CESL). The dielectric layer 156 may include anysuitable dielectric material, such as a nitrogen-containing dielectricmaterial, an oxygen-containing dielectric material, other suitablematerials, or combinations thereof. In the depicted embodiment, thedielectric layer 156 includes a nitrogen-containing dielectric material,such as silicon nitride, carbon-doped silicon nitride, or a metalnitride. The dielectric material(s) included in the gate spacer layer154 is different from the dielectric material(s) included in thedielectric layer 156, such that the gate spacer layer 154 may be etchedrelative to the dielectric layer 156 at a subsequent fabrication step.In some embodiments, the dielectric material(s) included in thedielectric layer 156 is similar to those included in the gate spacerlayer 152. In many embodiments, the dielectric layer 156 may be formedby any suitable method, such as ALD, CVD, PVD, other suitable methods,or combinations thereof.

Referring to FIGS. 2 and 7, the method 200 at operation 208 replaces thedummy gate structures 140 with HKMGs 170. As depicted herein, the HKMGs170 replacing the dummy gate structures 140A are referred to as HKMGs170A, those replacing the dummy gate structures 140B are referred to asHKMGs 170B, and the HKMG replacing the dummy gate structure 140C isreferred to as HKMG 170C. Before replacing the dummy gate structures 140with HKMGs 170, the method 200 first deposits an interlayer dielectric(ILD) layer 158 over the semiconductor structure 100. The ILD layer 158may include any suitable dielectric material, such astetraethylorthosilicate (TEOS), un-doped silicate glass, or dopedsilicon oxide such as borophosphosilicate glass (BPSG), fused silicaglass (FSG), phosphosilicate glass (PSG), boron doped silicon glass(BSG), other suitable dielectric materials, or combinations thereof. TheILD layer 158 may include a multi-layer structure having multipledielectric materials. The ILD layer 158 may be deposited by a processsuch as, for example, CVD, PVD, ALD, flowable CVD (FCVD), spin-on-glass,other suitable methods. Subsequent to depositing the ILD layer 158, aplanarization process such as CMP may be performed to remove excess ILDlayer 158 as well as the hard mask layers 144 and 146, such that, amongother things, top portions of the gate spacer layer 154 are exposed inthe device region 110A but not in the isolation region 110B.

Thereafter, still referring to FIG. 7, the method 200 at operation 208removes the dummy gate structures 140 to form gate trenches (notdepicted) in both the device region 110A and the isolation region 110B.In some embodiments, forming the gate trenches includes performing anetching process that selectively removes the dummy gate structures 140relative to the gate spacer layers 152 and 154, the dielectric layer156, and the ILD layer 158. In other words, the etching process may betuned such that the etching of the dummy gate structures 140 issubjected to a higher etch rate relative to the gate spacer layers 152and 154, the dielectric layer 156, and the ILD layer 158. The etchingprocess may be a dry etching process, a wet etching process, an RIE,other suitable methods, or combinations thereof. The dry etching processmay use any suitable etchant, such as chlorine-containing gases,fluorine-containing gases, other etching gases, or combinations thereof.The wet etching solutions may include ammonium hydroxide (NH₄OH),hydrofluoric acid (HF) or diluted HF, deionized water,tetramethylammonium hydroxide (TMAH), other suitable wet etchingsolutions, or combinations thereof. In an example embodiment, a dryetching process may be implemented to remove the dummy gate structures140.

Thereafter, the method 200 at operation 208 forms HKMGs 170 in the gatetrenches to complete the gate replacement process. Each of the HKMGs 170(i.e., 170A, 170B, or 170C) includes at least a high-k dielectric layer(e.g., having a dielectric constant greater than that of silicon oxide;not depicted) and a conductive electrode (not depicted) that furtherincludes at least one work function metal layer and a bulk conductivelayer. The high-k dielectric layer may include hafnium oxide (HfO₂),zirconium oxide (ZrO₂), lanthanum oxide (La₂O₃), titanium oxide (TiO₂),yttrium oxide (Y₂O₃), strontium titanate (SrTiO₃), other suitablemetal-oxides, or combinations thereof. The work function metal layer mayinclude a p-type or an n-type work function material, such as TiN, TaN,Ru, Mo, Al, WN, ZrSi₂, MoSi₂, TaSi₂, NiSi₂, WN, Ti, Ag, TaAl, TaAlC,TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable materials, orcombinations thereof. The bulk conductive layer may include Cu, W, Al,Ru, Co, other suitable metals, or combinations thereof. Each of theHKMGs 170 may further includes additional material layers, such as aninterfacial layer, a barrier layer, a hard mask layer, other suitablelayers, or combinations thereof. Various material layers of the HKMG 170may be formed by chemical oxidation, CVD, ALD, PVD, FCVD, plating, othersuitable methods, or combinations thereof. A CMP process may beperformed to remove excess materials from the HKMGs 170 so as toplanarize a top surface of the semiconductor structure 100 following thegate replacement process.

Referring to FIGS. 2 and 8, the method 200 at operation 210 removes thegate spacer layer 154 to form trenches (also referred to as air gaps)180 along sidewalls of the HKMGs 170A in an etching process 164. In manyembodiments, the method 200 selectively removes the gate spacer layer154 relative to the gate spacer layer 152, the dielectric layer 156, theILD layer 158, and the HKMGs 170. In other words, the etching of thegate spacer layer 154 is subjected to a higher rate relative to the gatespacer layer 152, the dielectric layer 156, the ILD layer 158, and theHKMGs 170. The etching process 164 may be tuned in a similar fashion asthe etching process 162, such as by controlling etching power, dutycycle, duration of etching time, and/or ratio of multiple etchants.Specifically, the etching process 164 removes the gate spacer layer 154disposed on both sidewalls of the HKMGs 170A and on one of the twosidewalls of the HKMG 170C, leaving behind the gate spacer layer 154still disposed on the other one of the tw sidewalls of the HKMG 170C.Notably, because the dielectric layer 156 is deposited over theremaining portions 182 and 184 of the gate spacer layer 154, the gatespacer layer 154 disposed on both sidewalls of the HKMGs 170B and on oneof the sidewalls of the HKMG 170C remain after the etching process 164is performed. Stated in a different way, the dielectric layer 156disposed in the isolation region 110B protects the underlying remainingportions 182 and 184 of the gate spacer layer 154 from being removedduring the etching process 164. In some embodiments, reduction incapacitance of devices is ensured when the gate spacer layer 154 isremoved completely formed sidewalls of the HKMGs 170 in the deviceregion 110A.

In some embodiments, the etching process 164 may implement any suitableetching process, such as a dry etching process, a wet etching process,RIE, other suitable processes, or combinations thereof. In an exampleembodiment, the etching process 164 implements a dry etching processusing one or more suitable etchant, such as a fluorine-containingetchant, a chlorine-containing etchant, other suitable etchants, orcombinations thereof. In some embodiments, the etching process 164 isimplemented anisotropically along the Z direction. The resulting air gap180 has a height substantially similar (e.g., within ±2%) to a height ofthe HKMGs 170A and 170C but less than (e.g., about 50% to about 80%) aheight of the fin 120 over which it is disposed.

Referring to FIGS. 2 and 9, the method 200 at operation 212 formscontact features 172 in the device region 110A and contact features 174in the isolation region 110B. Specifically, the contact features 172 areformed between adjacent HKMGs 170A and/or 170C, such that the contactfeatures 172 are disposed over the S/D features 122 and electricallycouple the S/D features 122 to conductive features (e.g., via contacts,conductive lines, etc.) formed hereafter. Thus, the contact features 172may be referred to as device-level contacts. In the depicted embodiment,sidewalls of the contact features 172 are defined by the dielectriclayer 156 and the ILD layer 158. However, the present disclosure is notlimited to this configuration. For example, the ILD layer 158 may beabsent along sidewalls of the contact features 172. In the isolationregion 110B, the contact features 174 are formed between adjacent HKMGs170B and 170C and between adjacent HKMGs 170B. In the depictedembodiment, a bottom surface and sidewalls of the contact features 174are defined by the ILD layer 158, such that the bottom surface of thecontact features 174 does not physically contact the dielectric layer156 disposed in the isolation region 110B. However, the presentdisclosure is not limited to this configuration. For example, the bottomsurface of the contact features 174 may be in contact with thedielectric layer 156.

The contact features 172 and 174 may each include any suitableconductive material, such as Cu, W, Al, Ru, Co, other suitable metals,or combinations thereof. The contact features 172 and 174 may be formedby a series of patterning and etching processes. For example, apatterned mask (not depicted) may be formed over the semiconductorstructure 100 to expose regions between adjacent HKMGs 170 (e.g.,adjacent HKMGs 170A, adjacent HKMGs 170B, and/or adjacent HKMGs 170C).Then, one or more etching process may be performed to remove at leastportions of the ILD layer 158 to form contact trenches (not depicted) inwhich the contact features 172 and 174 may be formed. The etchingprocess may include one or more dry etching process, wet etchingprocess, RIE, other suitable methods, or combinations thereof.Thereafter, one or more suitable conductive material may be formed inthe contact trenches using any suitable method, such as CVD, ALD, PVD,plating, other suitable methods, or combinations thereof. In thedepicted embodiment, portions of the ILD layer 158 remain alongsidewalls of the contact features 172. However, the present disclosurealso provides embodiments in which the ILD layer 158 is completelyremoved from the contact trenches, such that no ILD layer 158 remainsalong sidewalls of the contact features 172. A CMP process may beperformed to remove excess conductive material, such that a top surfaceof the semiconductor structure 100 may be planarized. Thereafter, an ILDlayer 178 may be formed over the semiconductor structure 100 toaccommodate further processing steps.

Furthermore, the height h_(s) and the height h_(p) of the remainingportions 184 and 182, respectively, remain substantially unchanged fromthe embodiment discussed in reference to FIG. 5. For example, the heighth_(s) is at least about 30% the height h₂ of the HKMGs 170B, and theheight h_(p) is greater than the fin height h_(f).

In some embodiments, a dielectric layer 166 is formed over a top surfaceof the HKMGs 170, the gate spacer layer 152, the trenches (or air gaps)180, the dielectric layer 156, and portions of the ILD layer 158 priorto performing the patterning and etching processes to form the contactfeatures 172 and 174. The dielectric layer 166 may include any suitabledielectric material, such as a nitrogen-containing dielectric material,an oxygen-containing dielectric material, other suitable materials, orcombinations thereof. In the depicted embodiment, the dielectric layer166 includes a nitrogen-containing dielectric material, such as siliconnitride or a metal nitride. The dielectric material(s) included in thedielectric layer 166 may be the same or different from the dielectricmaterial included in the dielectric layer 156, and may be formed by anysuitable method, such as ALD, CVD, PVD, other suitable methods, orcombinations thereof. In some embodiments, the dielectric layer 166 isformed at a lower processing temperature than other dielectriccomponents of the semiconductor structure 100 due to it needing a lowerthermal budget after the formation of the HKMGs 170, having a lowerdielectric constant that other dielectric components (e.g., thedielectric layer 156), and exhibiting a relatively higher throughoutduring production. In one such example, the dielectric layer 166 may beformed at a temperature from about 300 degrees Celsius to about 450degrees Celsius.

Subsequently, at operation 214, the method 200 performs additionalprocessing steps to the semiconductor structure 100. For example,additional vertical interconnect features such as vias (e.g., viasconfigured to electrically connect with the contact features 172 and174) and/or horizontal interconnect features such as lines, andmultilayer interconnect features such as metal layers and interlayerdielectrics can be formed over the semiconductor structure 100. Thevarious interconnect features may implement various conductive materialsincluding copper (Cu), tungsten (W), cobalt (Co), aluminum (Al),titanium (Ti), tantalum (Ta), platinum (Pt), molybdenum (Mo), silver(Ag), gold (Au), manganese (Mn), zirconium (Zr), ruthenium (Ru), theirrespective alloys, metal silicides, and/or other suitable materials. Themetal silicides may include nickel silicide, cobalt silicide, tungstensilicide, tantalum silicide, titanium silicide, platinum silicide,erbium silicide, palladium silicide, and/or other suitable metalsilicides.

Although not intended to be limiting, one or more embodiments of thepresent disclosure provide many benefits to a semiconductor device andthe formation thereof. For example, embodiments of the presentdisclosure provide methods for forming air gap on sidewalls of HKMGs inan active device region of a semiconductor structure but not in anisolation region (e.g., shallow-trench isolation structures) of thesemiconductor structure. Many embodiments of the present disclosureimprove performance of the HKMGs in the active device region is reducedby including the air gap in place or as a part of the gate spacer whilemaintaining structural integrity of HKMGs in the isolation region byexcluding the air gap from the gate spacer.

In one aspect, the present disclosure provides a method that includesproviding dummy gate structures disposed over an active region and overan isolation region adjacent the active region, a first gate spacerdisposed along sidewalls of the dummy gate structures in the activeregion, and a second gate spacer disposed along sidewalls of the dummygate structures in the isolation region, removing top portions of thesecond gate spacer, but not the first gate spacer, forming a firstdielectric layer over the first gate spacer and remaining portions ofthe second gate spacer, replacing the dummy gate structures with metalgate structures after the forming of the first dielectric layer,removing the first gate spacer, after the replacing of the dummy gatestructures, and forming a second dielectric layer over top surfaces ofthe metal gate structures and of the first dielectric layer.

In some embodiments, the first and the second gate spacers include thesame composition.

In some embodiments, removing the top portions of the second gate spacerincludes forming a patterned mask over the active region, therebyexposing the isolation region, and selectively etching the top portionsof the second gate spacer relative to the dummy gate structures in theisolation region.

In some embodiments, removing the top portions of the second gate spacerincludes removing no more than about 70% of a height of the second gatespacer.

In some embodiments, removing the first gate spacer includes forming anair gap disposed between sidewalls of the metal gate structures and thefirst dielectric layer in the active region, and wherein the forming ofthe second dielectric layer includes sealing the air gap.

In some embodiments, removing the first gate spacer includes selectivelyetching the first gate spacer relative to the first dielectric layer.

In some embodiments, the active region includes source/drain featuresdisposed therein, and the method further includes, after the forming ofthe second dielectric layer, forming source/drain contacts over thesource/drain features, where the source/drain contacts are disposedbetween the metal gate structures.

In another aspect, the present disclosure provides a semiconductorstructure that includes a first metal gate structure disposed over afin, a second metal gate structure disposed over an isolation regionadjacent the fin, a gate spacer disposed on a bottom portion ofsidewalls of the second metal gate structure, where a top portiondisposed above the bottom portion of the second metal gate structure isfree of the gate spacer, a first dielectric layer disposed on sidewallsof the first metal gate structure and on the sidewalls of the secondmetal gate structure, where the first dielectric layer directly contactsthe gate spacer, a second dielectric layer disposed over the first metalgate structure and the first dielectric layer that seals an air gapdisposed between the first dielectric layer and the sidewalls of thefirst metal gate structure, and S/D contacts disposed over S/D features,which are disposed over the fin.

In some embodiments, the gate spacer is a first gate spacer and the airgap is a first air gap, and the semiconductor structure further includesa third metal gate structure disposed over the fin and between the firstand the second metal gate structures, the third metal gate structureincluding a first sidewall and a second sidewall, and a second gatespacer disposed over the isolation region and on a bottom portion of thesecond sidewall, where a top portion disposed above the bottom portionof the second sidewall is free of the second gate spacer, where thefirst dielectric layer is disposed on the first and the secondsidewalls, where the first dielectric layer is separated from the firstsidewall by a second air gap, and where the first dielectric layerdirectly contacts the second gate spacer. In a further embodiment, thesecond air gap and the first air gap have the same height.

In some embodiments, a height of the air gap is substantially similar toa height of the first metal gate structure. In some embodiments, aheight of the air gap is less than a height of the fin.

In some embodiments, a top surface of the gate spacer is above a topsurface of the fin. In some embodiments, a height of the gate spacer isabout at least 30% of a height of the second metal gate structure.

In yet another aspect, the present disclosure provides a semiconductorstructure that includes a high-k metal gate structure (HKMG) disposedover an isolation feature of a substrate, where a top portion disposedabove the bottom portion of the sidewalls of the HKMG is free of thegate spacer layer, a gate spacer layer disposed on and directlycontacting a bottom portion of sidewalls of the HKMG, a dielectric layerdirectly contacting the gate spacer layer and the top portion of thesidewalls of the HKMG, and a conductive feature disposed adjacent theHKMG in an interlayer dielectric (ILD) layer, where the ILD layerseparates the conductive feature from the dielectric layer.

In some embodiments, the HKMG is a first HKMG, and the semiconductorstructure further includes an active region disposed adjacent theisolation feature over the substrate and a second HKMG disposed over afin in the active region, wherein sidewalls of the second HKMG are freeof the gate spacer layer. In a further embodiment, a top surface of thegate spacer layer is above a top surface of the fin. In someembodiments, the dielectric layer is disposed on and separated from thesidewalls of the second HKMG by an air gap.

In still further embodiments, the semiconductor structure includes athird HKMG disposed over the active region, where a first sidewall andan upper portion of a second sidewall opposite the first sidewall of thethird HKMG are free of the gate spacer layer, and where the gate spacerlayer is disposed on a bottom portion of the second sidewall of thethird HKMG.

In some embodiments, the dielectric layer is disposed over and separatedfrom the first sidewall by an air gap, and the dielectric layer isdisposed over and physically contacting the second sidewall.

The foregoing outlines features of several embodiments so that those ofordinary skill in the art may better understand the aspects of thepresent disclosure. Those of ordinary skill in the art should appreciatethat they may readily use the present disclosure as a basis fordesigning or modifying other processes and structures for carrying outthe same purposes and/or achieving the same advantages of theembodiments introduced herein. Those of ordinary skill in the art shouldalso realize that such equivalent constructions do not depart from thespirit and scope of the present disclosure, and that they may makevarious changes, substitutions, and alterations herein without departingfrom the spirit and scope of the present disclosure.

What is claimed is:
 1. A method, comprising: providing dummy gatestructures disposed over an active region and over an isolation regionadjacent to the active region, a first gate spacer disposed alongsidewalls of the dummy gate structures over the active region, and asecond gate spacer disposed along sidewalls of the dummy gate structuresover the isolation region; removing top portions of the second gatespacer, but not the first gate spacer; forming a first dielectric layerover the first gate spacer and remaining portions of the second gatespacer; after forming the first dielectric layer, replacing the dummygate structures with metal gate structures; after replacing the dummygate structures, removing the first gate spacer; and forming a seconddielectric layer over top surfaces of the metal gate structures and thefirst dielectric layer.
 2. The method of claim 1, wherein the first andthe second gate spacers include the same composition.
 3. The method ofclaim 1, wherein removing the top portions of the second gate spacerincludes: forming a patterned mask over the active region, therebyexposing the isolation region; and selectively etching the top portionsof the second gate spacer relative to the dummy gate structures over theisolation region.
 4. The method of claim 1, wherein removing the topportions of the second gate spacer includes removing no more than about70% of a height of the second gate spacer.
 5. The method of claim 1,wherein removing the first gate spacer includes forming an air gapdisposed between sidewalls of the metal gate structures and the firstdielectric layer over the active region, and wherein the forming of thesecond dielectric layer includes sealing the air gap.
 6. The method ofclaim 1, wherein removing the first gate spacer includes selectivelyetching the first gate spacer relative to the first dielectric layer. 7.The method of claim 1, wherein the active region includes source/drainfeatures disposed therein, the method further comprising, after theforming of the second dielectric layer, forming source/drain contactsover the source/drain features, the source/drain contacts being disposedbetween the metal gate structures.
 8. A method, comprising: providing aworkpiece comprising first dummy gate structures disposed directly on anisolation feature, first gate spacer layers extending along sidewallsurfaces of the first dummy gate structures, and second gate spacerlayers extending along sidewall surfaces of the first gate spacerlayers; selectively recessing the second gate spacer layers withoutsubstantially etching the first gate spacer layers; conformallydepositing a first dielectric layer over the workpiece; depositing asecond dielectric layer over the first dielectric layer; and replacingthe first dummy gate structures with metal gate stacks.
 9. The method ofclaim 8, wherein the first gate spacer layers comprise a lower portionin direct contact with the recessed second gate spacer layers and anupper portion in direct contact with the first dielectric layer.
 10. Themethod of claim 8, wherein the first gate spacer layers comprise agreater amount of carbon than the recessed second gate spacer layers.11. The method of claim 8, wherein the workpiece further comprises: afin-shaped active region adjacent the isolation feature; second dummygate structures over channel regions of the fin-shaped active region;source/drain features coupled to the channel regions; third gate spacerlayers extending along sidewall surfaces of the second dummy gatestructures; and fourth gate spacer layers extending along sidewallsurfaces of the third gate spacer layers; wherein heights of the seconddummy gate structures are less than heights of the first dummy gatestructures.
 12. The method of claim 11, further comprising: replacingthe second dummy gate structures with metal gate stacks; and selectivelyremoving the fourth gate spacer layers to form air gaps exposingsidewall surfaces of the third gate spacer layers.
 13. The method ofclaim 11, wherein top surfaces of the recessed second gate spacer layersare above a top surface of the fin-shaped active region.
 14. A method,comprising: providing a workpiece comprising first dummy gate structuresengaging an active region and second dummy gate structures directly overan isolation feature adjacent to the active region, a first gate spacerlayer disposed along sidewalls of the first dummy gate structures, and asecond gate spacer layer disposed along sidewalls of the second dummygate structures; performing an etching process to selectively recess thesecond gate spacer layer; selectively removing the first dummy gatestructures and the second dummy gate structures to form gate trenches;forming metal gate stacks in the gate trenches; and after the forming ofthe metal gate stacks, selectively removing the first gate spacer layerto form air gaps over the active region.
 15. The method of claim 14,wherein the selectively recessing of the second gate spacer layercomprises: forming a patterned mask over the workpiece, the patternedmask covering the first gate spacer layer and exposing the second gatespacer layer; and selectively removing top portions of the second gatespacer layer relative to the second dummy gate structures.
 16. Themethod of claim 14, after the performing of the etching process, a topsurface of a remaining portion of the second gate spacer layer is abovea top surface of the active region.
 17. The method of claim 14, furthercomprising: before the selectively removing of the first dummy gatestructures and the second dummy gate structures, depositing a firstdielectric layer over the workpiece, wherein the first dielectric layercovers the first gate spacer layer and a remaining portion of the secondgate spacer layer; depositing a second dielectric layer over the firstdielectric layer; and performing a planarization process to theworkpiece to expose a top surface of gate electrodes in the first andsecond dummy gate structures and expose the first gate spacer layerwithout exposing the remaining portion of the second gate spacer layer.18. The method of claim 14, wherein a top surface of the isolationfeature is below a top surface of the active region and comprises aconcave surface.
 19. The method of claim 14, wherein heights of portionsof the metal gate stacks over the isolation feature are greater thanheights of portions of the metal gate stacks over the active region. 20.The method of claim 14, wherein each of the first gate spacer layer andthe second gate spacer layer comprises a multi-layer structure thatincludes a first layer and a second layer extending along a sidewallsurface of the first layer, wherein the performing of the etchingprocess selectively recesses the second layer of the second gate spacerlayer without substantially etching the first layer of the second gatespacer layer.